2026 · APR · 18 → 20 · 3 DAYS · T4 → L4
230 GB/s on T4. But the real bottleneck wasn't the kernel — it was the copy across PCIe.
One reason D2H is 12.7× slower. And the 5.6× end-to-end gap.
Shared memory, warp shuffle, and the 29% a single __syncthreads bought.
0.4 → 7.9 TFLOPS. A 20× roofline journey, in four layers.
Fuse three kernels into one and get exactly 2× speedup. The birth of online softmax.
4.79× faster at N=4096, 65× less HBM traffic. And the line we hit.
torch.ops.mylib.flash_attention. From this moment on, vLLM source becomes readable.
Jump to L4. Four kernels into Triton. Found a zone where we narrowly beat cuBLAS.
4-D shape + causal + torch.compile(fullgraph=True). 80–90% of cuDNN FA-2.
Beyond "fast/slow," reading lessons 1–9 through lg_throttle, wait, math_pipe_throttle.
contiguous → paged. A GQA grid refactor beats cuDNN FA-2 by 14 %. Axis-for-axis match with vLLM source.
ctx-axis partition + reduce kernel. 1.68× speedup. Remaining gap is L2 residency.
Can 50 lines replace 5000? The answer from four kernels.
IS_CAUSAL: tl.constexpr, loop-skip, custom_op. Three tricks combined.
Sam × Jensen (fictional). Replay the 7-week path in reverse and Flash Attention looks inevitable.
Seven files side by side, line by line. When CUDA folds into Triton, what vanishes and what remains.